`timescale 1ns / 1ps
//****************************************VSCODE PLUG-IN**********************************//
//----------------------------------------------------------------------------------------
// IDE :                   VSCODE     
// VSCODE plug-in version: Verilog-Hdl-Format-2.4.20240526
// VSCODE plug-in author : Jiang Percy
//----------------------------------------------------------------------------------------
//****************************************Copyright (c)***********************************//
// Copyright(C)            Please Write Company name
// All rights reserved     
// File name:              
// Last modified Date:     2024/05/28 16:06:37
// Last Version:           V1.0
// Descriptions:           
//----------------------------------------------------------------------------------------
// Created by:             Please Write You Name 
// Created date:           2024/05/28 16:06:37
// mail      :             Please Write mail 
// Version:                V1.0
// TEXT NAME:              img_get_from_ddr.v
// PATH:                   D:\FPGA\frame_difference_multi_moving_detection\rtl\img_processor\img_processing\img_get_from_ddr.v
// Descriptions:           
//                         
//----------------------------------------------------------------------------------------
//****************************************************************************************//

module img_get_from_ddr #(
    parameter
        FRAME_ROW               = 16'd480,
        FRAME_LINE              = 16'd640,
        IMG_GET_FREAME_LIMITE   = 16'd2  
)(
    input                               clk                         , // 用img时钟 48M
    input                               rst_n                       ,
    input                               img_href                    ,
    input                               img_vsync                   ,
    input   [15:0]                      fifo_rd_img_data            ,
    output                              input_fifo_rd_en            ,
    output                              img_vsync_o                 ,
    output                              img_href_o                  ,
    output  [15:0]                      img_data_o                  ,
    output reg                          img_data_valid              

);
//reg define
reg [15:0] frame_cnt;
reg [15:0] img_href_cnt;
reg [15:0] fifo_en_cnt;
reg img_vsync_d1;
reg img_href_d1;
//wire define
wire img_vsync_pos;
wire img_href_pos;
wire img_href_w;
//---------------------------------< main code >----------------------------------
//---------------------------------<  组合逻辑  >----------------------------------
assign img_vsync_pos = img_vsync & (~img_vsync_d1);
assign img_href_pos = img_href & (~img_href_d1);
assign img_data_o = fifo_rd_img_data;
//---------------------------------<  时序逻辑  >----------------------------------
// 对帧计数，在第二帧后，图像输出数据与ov5640现帧数据保持一帧时差输出(输出是16bit的，img_data从0v5640出来的是8位数据，因此这里在两个时钟内只输出一个16bit)
assign input_fifo_rd_en = ((frame_cnt == IMG_GET_FREAME_LIMITE) && (img_href_cnt[0] == 1'd0) && (img_href_cnt != (FRAME_LINE << 1) - 16'd1) && img_href) ? 1'd1 : 1'd0;
assign img_href_o       = (frame_cnt == IMG_GET_FREAME_LIMITE) ? img_href_d1 : 1'd0;  // 时序同步
assign img_vsync_o      = (frame_cnt == IMG_GET_FREAME_LIMITE) ? img_vsync_d1 : 1'd0; // 时序同步

// img_data_valid
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        img_data_valid <= 1'd0;
    else if(img_href_o)
        img_data_valid <= ~img_data_valid;
    else
        img_data_valid <= 1'd0;
end

always @(posedge clk or negedge rst_n) begin // 第一帧以后，frame_cnt稳定在2
    if(~rst_n)
        frame_cnt <= 16'd0;
    else if(frame_cnt == IMG_GET_FREAME_LIMITE)
        frame_cnt <= frame_cnt;
    else if(img_vsync_pos)
        frame_cnt <= frame_cnt + 1'd1;
    else ;
end

// href / vsync / img_href_o打拍
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)begin
        img_vsync_d1 <= 1'd0;
        img_href_d1 <= 1'd0;
    end
    else begin
        img_vsync_d1 <= img_vsync;
        img_href_d1 <= img_href;
    end
end

// img_href_cnt
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
        img_href_cnt <= 16'd0;
    else if(img_href_cnt == (FRAME_LINE << 1) - 16'd1)
        img_href_cnt <= 16'd0;
    else if((frame_cnt == IMG_GET_FREAME_LIMITE) && img_href)
        img_href_cnt <= img_href_cnt + 16'd1;
    else ;
end
endmodule